Multiple bus architecture - computer architecture, Computer Engineering

Multiple bus architecture:

One solution to the bandwidth restriction of a single bus is to simply add extra buses. Consider the architecture indicated in given figure that contains N processors, P1 P2 PN, each containing its own private cache, and all linked to a shared memory by B buses BB, B1, B2. The shared memory consists of M interleaved banks M1 M2,MM to permit simultaneous memory requests concurrent access to the shared memory. It ignores the loss in performance that happen if those accesses have to be serialized, which is the case when there is only 1 memory bank. Each processor is linked to every bus and so is each memory bank. When a processor requires accessing a specific bank, it has B buses from which to select. Therefore each processor- memory pair is linked by various redundant paths, which implies that the failure of 1 or more paths can, principally, be tolerated at the cost of some degradation in system performance.

In a multiple bus system many processors may try to access the shared memory simultaneously. To deal with this problem, a policy might be implemented that allocates the available buses to the processors making requests to memory. In particular case, the policy might deal with the case when the number of processors exceeds from the B. For performance point of view this allocation has to be performed by hardware arbiters which, as we will see, add significantly to the difficulty of the multiple bus interconnection networks.

PCout, R=B, MARin, Read, IncPC

  • WFMC
  • MDRoutB, R=B, IRin
  • R4out, R5outB, SelectA, Add, R6in, End.

389_Multiple bus architecture.png

Posted Date: 10/13/2012 6:48:37 AM | Location : United States







Related Discussions:- Multiple bus architecture - computer architecture, Assignment Help, Ask Question on Multiple bus architecture - computer architecture, Get Answer, Expert's Help, Multiple bus architecture - computer architecture Discussions

Write discussion on Multiple bus architecture - computer architecture
Your posts are moderated
Related Questions
Information Technology or Information System Before going further we need to clarify what we mean by the term information system. It is easy to confuse terminology as many tex

Why do we need Registers? If t cpu is cycle time of CPU which is the time taken by CPU to execute a well-defined micro-operation employing registers and t mem is memory cycl

Memory-to-Memory Architecture : The pipelines can access vector operands, intermediate and final results directly in the main memory. This needs the higher memory bandwidth. How

What is meant by bitwise operations? C has distinction of supporting special operators known as bit wise operators for manipulation of data at bit level. These operators are us

Why pointer variable sometimes desirable to pass a pointer to a function as an argument? Frequently, a called function needs to make changes to objects declared in the calling

Define about Abstraction-  object oriented systems Abstraction is one of the most important ideas of object oriented systems Abstraction focus on the necessary, inherent aspec

Define dynamic loading. To get better memory-space utilization dynamic loading is used. With dynamic loading, a routine is not loaded unless it is called. All routines are kept

Q. Explain about Micro-instruction Formats? Now let's focus on format of a micro-instruction. The two widely used formats employed for micro-instructions are vertical and horiz

Real Life Business Subsystems A Subsystem is a component of a System even though it can also be described as a system in its own right. Consider a manufacturing firm. It compr

The number of control lines for 32 to 1 multiplexer is ? Ans. For 32 (2 5 ) the number of control lines and to select one i/p between them total 5 select lines are needed.