Multiple bus architecture - computer architecture, Computer Engineering

Multiple bus architecture:

One solution to the bandwidth restriction of a single bus is to simply add extra buses. Consider the architecture indicated in given figure that contains N processors, P1 P2 PN, each containing its own private cache, and all linked to a shared memory by B buses BB, B1, B2. The shared memory consists of M interleaved banks M1 M2,MM to permit simultaneous memory requests concurrent access to the shared memory. It ignores the loss in performance that happen if those accesses have to be serialized, which is the case when there is only 1 memory bank. Each processor is linked to every bus and so is each memory bank. When a processor requires accessing a specific bank, it has B buses from which to select. Therefore each processor- memory pair is linked by various redundant paths, which implies that the failure of 1 or more paths can, principally, be tolerated at the cost of some degradation in system performance.

In a multiple bus system many processors may try to access the shared memory simultaneously. To deal with this problem, a policy might be implemented that allocates the available buses to the processors making requests to memory. In particular case, the policy might deal with the case when the number of processors exceeds from the B. For performance point of view this allocation has to be performed by hardware arbiters which, as we will see, add significantly to the difficulty of the multiple bus interconnection networks.

PCout, R=B, MARin, Read, IncPC

  • WFMC
  • MDRoutB, R=B, IRin
  • R4out, R5outB, SelectA, Add, R6in, End.

389_Multiple bus architecture.png

Posted Date: 10/13/2012 6:48:37 AM | Location : United States







Related Discussions:- Multiple bus architecture - computer architecture, Assignment Help, Ask Question on Multiple bus architecture - computer architecture, Get Answer, Expert's Help, Multiple bus architecture - computer architecture Discussions

Write discussion on Multiple bus architecture - computer architecture
Your posts are moderated
Related Questions
Fuzzy Logic: In the logics we are here described above, what we have been concerned with truth: whether propositions and sentences are true. Moreover, with some natural langua

a) Prototype a macro known AP which takes 4 integer parameters n (number of terms), a (first term), l (last term) and Sum (sum of n terms), provided that: Sum = (a+l)*n/2 b)

Q. Block Format and Disk Layout on CD-ROM? A typical block format is displayed in Figure (a). It comprises the subsequent fields: Sync: Sync field identifies beginning o

Ease of Learning - User Friendliness Much has been made recently of increasing sophistication in technology with one of the major benefits advertised as an increase in somethi

The three main elements of LDB are:- Structure Selections and Database Program.

Q. Determine the performance of a parallel algorithm? One more method of determining the performance of a parallel algorithm can be performed after calculating a parameter know

In a word,you can't. It would certainly be helpful to be able to color-code your worksheet tabs. For some reason, Microsoft hasn't executed this feature, which has been available i

In a two stage network there are 512 inlets and outlets, r=s=24. If the probability that a given inlet is active is 0.8, calculate: Blocking probability Given: N =M =512,

Memory utilization factor shall be computed as? Ans. memory in use/total memory connected.

Which one is better hardware or software firewall While deciding whether to buy a hardware or software firewall, the user must consider important factors such as performance an