When constructing a NAND gate using transistors as the switching devices, the output often represents the 'inversion' of the "AND" gate. Figure 4 shows an example of a 2 input digital gate consisting of two NPN transistors, TR1 and TR2, which are assumed to be perfect switches. In a positive logic system, when input A and input B are both at the 0 state (0v), both transistors are biased OFF and the output will adopt the 1 state (+ 5v). If input A only is now given the 1 state, transistor TR1 is biased ON but no collector current can flow as TR2 is still OFF. Similarly, if input B only is given the 1 state then transistor TR2 is biased ON but again no current can flow as TR1 is OFF. Only when both input A and input B are at the 1 state together, with both transistors ON, will current be allowed to flow taking the output to the 0 state.