Lift control unit, Electrical Engineering

You are required to design and document  the hardware design  for a 68HC12D60 based Lift Control Unit (LCU). This design includes  the Input/Output hardware for interfacing with  lift equipment, display, external memory and bus circuitry as described in questions below.

1.  Block Diagram

Draw a block diagram showing all the hardware components of the lift and the proposed lift control unit (including the I/O ports of the HC12), clearly showing the connection of signals between them.

2.  Microprocessor support

Draw a circuit diagram showing the minimum components needed to correctly operate the HC12  D60 microprocessor in normal expanded narrow mode.  (That is  -  for  external memory using an 8 bit data bus) You should ensure that:

(a)  power is provided to the HC12 (assume a regulated 5V supply is available)

(b)  interrupts are in their inactive condition

(c)  the microprocessor E clock operates at 8MHz

(d)  a reset circuit is provided.

(e)  data and address buffers/latches are used as required.

You must specify part numbers and suggest values for any components used.

3.  Memory Decoding

You must determine the amount of RAM required to meet the data storage requirements of the system for a 6 month operation of the lift. (Report your calculations for this as part of this question) Draw a circuit diagram  for  the  address decoding  hardware  required  to decode external memory  attached to  the HC12D60 microcontroller,  to match  the memory map  of figure 1. You must show how the E clock signal from a HC12 is used in the circuit to enable the decoders at the correct time in the microprocessor cycle. Clearly identify all ICs used, label all pins on all parts and label the signals coming to and from the parts.

Posted Date: 3/8/2013 4:37:19 AM | Location : United States







Related Discussions:- Lift control unit, Assignment Help, Ask Question on Lift control unit, Get Answer, Expert's Help, Lift control unit Discussions

Write discussion on Lift control unit
Your posts are moderated
Related Questions
The sinusoidal voltage source in the circuit shown in Fig. is developing an rms voltage of 2000 V. The 4 ? load in the circuit is absorbing four times as much average power as the

Draw and discuss power failure detection circuit interrupt NMI. The non-maskable interrupt (NMI) is an edge-triggered input which requests can interrupt upon the positive-edge.

Check Sheets - Quality Tools for Improvement This might be an easy listing of items that could represent information in an efficient, graphical format. If the system under ana

Q. Explain basic working of Transport Layer? It is responsible for establishing a network independent communication path appropriate for the specific terminal equipments (for exa

A voltage signal generated by a sensor conditioning circuit varies from -0.5V to +0.5V . The signal from the sensor is to be connected to the analog to digital  converter which onl

Conditional Call Instruction Similar  to conditional  jump  instructions there are conditional call  instructions  also based on various  flags.

DCR  Decrement Instruction This instruction  is used to decrement  the contents of any  register or memory  location by one. There are two  formats.

A photodiode is made to detect light quickly a solar cell is made to collect energy from light. They are both typically silicon diodes, but modified to meet their dissimilar requir

Explain SAHF instructions in 8086 family with example and their effect on flag. SAHF: Store AH register in flag register, this is an instruction utilized to store the data i

Design : Rather than 100 two-motion selectors as in the case of Design 3, let's consider only 24 two-motion selectors. In the case 24 simultaneous calls can be put through the swi