Instruction level-levels of parallel processing, Computer Engineering

Instruction Level

It refers to the condition where different instructions of a program are implemented by different processing elements. Most processors have numerous execution units and can execute some instructions (usually machine level) at the similar time. Good compilers can alter instructions to maximize instruction throughput. Often the processor also can do this. Modern processors still parallelize execution of micro-steps of instructions in the same pipe. The first use of instruction level parallelism in manipulative PE?s to enhance processing speed is pipelining.  Pipelining was widely used in early Reduced Instruction Set Computer (RISC).  Behind RISC, super scalar processors were developed which perform multiple instruction in one clock cycle. The super scalar processor plan exploits the parallelism accessible at instruction level by enhancing the number of functional and arithmetic units in PE?s.  The concept of teaching level parallelism was further customized and applied in the design of Very big Instruction Word (VLIW) processor, in which one instruction word encodes extra than one operation. The idea of executing a digit of instructions of a program in similar by scheduling them on a only processor has been a major driving power in the design of recent processors.

 

Posted Date: 3/1/2013 4:37:13 AM | Location : United States







Related Discussions:- Instruction level-levels of parallel processing, Assignment Help, Ask Question on Instruction level-levels of parallel processing, Get Answer, Expert's Help, Instruction level-levels of parallel processing Discussions

Write discussion on Instruction level-levels of parallel processing
Your posts are moderated
Related Questions
What is system testing? The final step in testing is system testing, which means checking the whole application. System testing exercises the overall application and make sure

is data bus is bidirectional

Q. Illustrate Clock signals of clock pulse generator? Synchronization in a sequential circuit is attained by a clock pulse generator that gives continuous clock pulse.  Figure

Write the truth table of NOR gate. Ans. The truth table for NOR gtae is shown below:

Returns the information about tasks running int info = pvm_tasks( int where, int *ntask, struct pvmtaskinfo **taskp ) struct pvmtaskinfo {  int ti_tid; int ti_pt

Question: (a) Copying a graphic image from the Web will be as easy as pointing to it and clicking the right mouse button or performing a screen capture. The question is, under

One can use the event GET in a report without LDB attribute. False. no one can use the event GET in a report without attribute.

A palindrome is a string that reads the same from both the ends. Given a string S convert it to a palindrome by doing character replacement. Your task is to convert S to palindrome

How do you create special files like named pipes and device files? The system call method forms special files in the following sequence. Kernel assigns new inode,

Digital circuits also manipulate logicalexpressione.g. IF account is in credit THEN allow phoneto make calls.So a digital circuit must determine if somethingis TRUE or FALSE. Norma