It refers to the condition where different instructions of a program are implemented by different processing elements. Most processors have numerous execution units and can execute some instructions (usually machine level) at the similar time. Good compilers can alter instructions to maximize instruction throughput. Often the processor also can do this. Modern processors still parallelize execution of micro-steps of instructions in the same pipe. The first use of instruction level parallelism in manipulative PE?s to enhance processing speed is pipelining. Pipelining was widely used in early Reduced Instruction Set Computer (RISC). Behind RISC, super scalar processors were developed which perform multiple instruction in one clock cycle. The super scalar processor plan exploits the parallelism accessible at instruction level by enhancing the number of functional and arithmetic units in PE?s. The concept of teaching level parallelism was further customized and applied in the design of Very big Instruction Word (VLIW) processor, in which one instruction word encodes extra than one operation. The idea of executing a digit of instructions of a program in similar by scheduling them on a only processor has been a major driving power in the design of recent processors.