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Q. Illustration of a memory organization?
Let's consider an illustration of a memory organization as displayed in Figure below in that main memory can store 32K words of 12 bits each one and cache is capable of storing 512 blocks (every block in present illustration is equal to 24 bits that is equal to two main memory words) at any instance.
Figure: Cache Memory
For each word stored in cache there is a duplicate copy in main memory. The CPU communicates with both memories. It first sends a 15 bits (32K =25 × 210 = 215) address to cache. If there is a hit then CPU uses relevant 12 bits data from 24 bit cache data. If there is a miss then CPU reads block containing relevant word from main memory. So key here is that a cache should store address and data portions of main memory to determine whether the given information is available in cache or not. But let's presume block size as 1 memory word for further discussions.
implementation of threads
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