The definitions of the bits in ICWI are following:
Always set to the value 1. It directs the received byte to ICWI as oppose to OCW2 or OCW3.
Which also utilize the even address (A0 = 0).
Bit 3 (LTIM) - Determines whether the level-triggered mode (LTIM = 1) or the edge-triggered mode (LTIM = 0) is to be utilized. The edge-triggered mode causes the IRR bit to be cleared while the corresponding ISR bit is set.
Bit 2 (ADD) - not utilized in an 8086/8088 system only used in an 8080 or 8085 system.
Bit 1 (SNGL) - denoted whether or not the 8259A is cascaded with other 8259As. SNGL = 1 when just one 8259A is in the interrupt system.
Bit 0 (IC4) - this is set to value 1 if an ICW4 is to be output to during the initialization sequence.
For an 8086/8088 system this bit ought to be always be set to 1 because bit 0 in JCW4 ought be set to 1.Bits 7-3 of ICW2 are tilled from bits 7-3 of the second byte output by the CPU during the initialization of the 8259A, and bits 2-0 are set accordingly the level of interrupt request, for instance a request on IR6 would cause them to be set to 110. ICW3 is important just in systems including more than one 8259A and is output to only if SNGL value is equal to 0. ICW4 is output to only if IC4 (ICWI) is set to value 1; or else, the contents of ICW4 are cleared. The bits in ICW4 are described as follows:
Bits 7-5 - it is always set to 0.
Bit 4 (SFNM) - If it is set to 1, the special fully nested mode is utilized. This mode is utilized in systems having more than one 8259A.
Bit 3 (BUF) - if BUF = 1 indicates that the SP/EN is to be utilized as an output to disable the system's8286 transceivers whereas the CPU inputs data from the 8259A. If no transceivers are present, then BUF should be set to value 0 and, in systems involving just one 8259A, a 1 should be applied to the SP/EN pin.
Bit 2 (M/S) - this bit is ignored when BUF value is zero. For a system that have only one 8259A, this bit should be1; or else, it should be the value1 for the master and value0 for the slaves.
Bit 1 (AEOI) - when AEOI = 1, then the ISR bit that caused the interrupt is cleared at the end of the second INTA pulse.
Bit 0 (µPM) - when µPM = 1 denote the 8259A is in an 8086/8088 system. This bit being 0 implies an 8085 or 8080 system. A usual program sequence for setting the contents of
ICWs, which suppose that the even address of the 8259A is 0080, is: MOV AL, 13H
OUT 80H, AL MOV AL, 18H
OUT 81H, AL MOV AL, ODH OUT 81H, AL
The first 2 instructions cause the requests to be edge triggered, show that only one 8259A which is used, and inform the 8259A that an ICW4 will be output. The next 2 instructions cause the 5 most important bits of the interrupt type to be set to value 00011. ICWS is not output to because SNGL = 1; so the final two instructions set ICW4 to OD, which informs the 8259A about the special wholly nested mode is not to be utilized, the SP/EN is utilized to disable transceivers, the 8259A is a master, EOI commands ought to be used to clear the ISR bit, and the 8259A is a part of the 8086 or 8088 system.