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Q. Explain about Control Memory Organization?
One of the simplest ways to organize control memory is to organize micro-instructions for different sub cycles of machine instruction in memory. The Figure below demonstrates such an organisation.
Figure: Control Memory Organisation
Let us give an illustration of control memory organization. Let's take a machine instruction: Branch on zero. This instruction causes a branch to a specified main memory address if result of the last ALU operation is zero which means zero flag is set. Pseudocode of micro-program for this instruction would be;
Test "zero flag" If SET branch to label ZERO
Unconditional branch to label NON-ZERO
ZERO: (Microcode that causes replacement of program counter with address offered in instruction)
Branch to interrupt or fetch cycle.
NON -ZERO: (Microcode that can set flags if desired indicating branch hasn't taken place).
Branch to interrupt or fetch cycle. (For Next- Instruction Cycle)
tCAS is the number of clock cycles required to access a particular column of data in SDRAM. CAS latency is the column address strobe time, sometimes referred to as tCL.
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