Ending transactions - data phase, Computer Engineering

Ending transactions:

Either side may request that a burst end after the present data phase. Simple PCI component that do not support multi-word bursts will always request this instantaneously. Even devices that do support bursts will have some restriction on the maximum length they can support, like as the end of their addressable memory.

The initiator can mark any data phase as the last one in a transaction by deserting FRAME# at the same time as it asserts IRDY#. The cycle after the target asserts TRDY#, the last data transfer is complete, both sides dessert their individual RDY# signals, and the bus is make idle again. The master may not dessert FRAME# before asserting IRDY#, nor may it assert FRAME# whereas it waiting, with IRDY# asserted, for the target to assert TRDY#.

The only minor exception is a master abort termination is happen when no target responds with DEVSEL#. Clearly, it is useless to wait for TRDY# in such type of case. However, even in this case, the master has to assert IRDY# for at least 1 cycle after deserting FRAME#. (Usually, a master will assert IRDY# before retain DEVSEL#, so it have to simply hold IRDY# asserted for 1 cycle longer.) It is to ensure that bus turnaround timing rules are obeyed on the FRAME# line.

The target requests the initiator end a burst by asserting STOP#. The initiator will then finish the transaction by deserting FRAME# at the next legal chance. If it desires to transfer any more data, it will continue in a separate transaction. There are various ways to do this:

Disconnect with data

If the target asserts TRDY # and STOP # at the same time, it indicates that the target wishes this to be the last data phase. For instance, a target that does not support burst transfers will always do it to force single-word PCI transactions. It is the most efficient way for a target to stop a burst.

Disconnect without data

If the target asserts STOP# without asserting TRDY#, it indicates that the target desire to stop without transferring data. STOP# is considered corresponding to TRDY# for the purpose of ending a data phase, but data is not transferred.


A Disconnection without data before transferring any data is a retry and unlike other type PCI transactions, PCI initiators are needed to pause slightly before continuing the operation. Observe the PCI specification for details.

Posted Date: 10/13/2012 7:35:28 AM | Location : United States

Related Discussions:- Ending transactions - data phase, Assignment Help, Ask Question on Ending transactions - data phase, Get Answer, Expert's Help, Ending transactions - data phase Discussions

Write discussion on Ending transactions - data phase
Your posts are moderated
Related Questions
Visibility. Controls should be clearly visible, so users can see the controls that are available to them. Visual feedback should also be clearly visible, so users can understand wh

Explain Performance Evaluation in parallel Computing In this section, we will discuss the key attributes used to measure performance of a computer system. The performance chara

Consider the situation in which the disk read/write head is currently located at track 45 (of tracks 0-255) and moving in the positive direction. Assume that the following track re

A museum has a collection of old posters advertising events of various kinds (theatre, sport, fairs, lectures etc.). It wishes to keep a record of these, containing, for each poste

A CSMA/CD bus spans a distance of 1.5 Km. If data is 5 Mbps, What is minimum frame size where propagation speed in LAN cable is 200 m µs. Usual propagation speed in LAN cables

Echo suppressor is detrimental to full duplex operation because? This disables one of the two pairs in a four-wire trunk line while a signal is detected upon another pair.

What are the steps in multiplication algorithm?   Check for zeros.   Multiply mantissas   Add the exponents.   Normalize the product.

You were offered bonus marks for separating the user interface code from the main logic of your program. This design choice makes it very easy to replace the user interface without

At time t when an infected machine scans and finds a vulnerable machine, the vulnerable one will be compromised and start to scan and infect others at time t+X, where X is a r.v. f

Programmable read only memory (PROM) A PROM is a memory chip on which data can be written only one time. Once a program has been written onto a PROM, it's permanent. Unlike RAM