electronic instrumentation and measurements, Electrical Engineering

why is a delay line used in the vertical selection of oscilloscope?
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Direct Addressing In this  addressing  mode one  of the  operands is the  data stored  in the memory. The memory  address of the  operand is directly  given in the instruction

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Q. For a BJT with vBE = 0.7V, I CBO = 4 nA, i E = 1 mA, and i C = 0.9 mA, evaluate α, iB,iSE, and β.

A coil of inductance 0.04 H and resistance 10? is connected to a 120 V, d.c. supply. Verify (a)  The final value of current     (b)  The time constant of the circuit (c)

what is bias compensation

Consider a CS JFET amplifier with the following parameters : R 1 = 350 k; R 2 = 100 k, R SS = 1200 , R D = 900 , R L = 1000 , R S = 2000 , ro = 15 k,gm = 6 × 10 -3 S,

D Flip Flop As we have seen  in the SR flip flop  when the inputs  S= R  are applied the forbidden or indeterminate state occurs.  This state can destabilize the SR file flop.

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Schematic Symbols The junction gate field-effect transistor or JFET gate is sometimes drawn in the middle of the channel (in place of at the drain or source electrode as in t