Design a mod-6 synchronous counter, Computer Engineering

Design a MOD-6 synchronous counter using J-K Flip-Flops.

Ans:

Design of Mod-6 Counter:  To design the Mod-6 synchronous counter, contain six counter states (that is, from 0 to 6). For this counter, the counter design table lists the three flip-flop and their states as 0 to 6 and the 6 inputs for the 3 flip-flops. The flip-flop inputs essential to step up the counter from the now to the next state is worked out along with the help of the excitation table.  The needed counter states and the J K inputs essential for counter flip- flops are specified in the counter design table demonstrated in Table no.1.

Input pulse

 

count

Counter States

 

Flip-Flop Inputs

 

A          B          C

 

JA

 

       KA

 

JB                KB

 

JC                  KC

0

0           0          0

1             X

0                 X

0                    X

1

1           0          0

X             1

1                 X

0                    X

2

0           1          0

1             X

X                 0

0                    X

3

1           1          0

X             1

X                 1

1                    X

4

0           0          1

1             X

0                 X

X                    0

5

1           0          1

X              1

0                 X

X                    1

6(0)

0           0         0

 

 

 

Table no.1: Counters Design Table for Mod-6 Counter

 Flip-Flop A:

The primary state is 0. This change to 1 after the clock pulses. Thus, JA must be 1 and KA may be 0 or 1 (that is X). In the subsequent state 1 change to 0 after the clock pulse.  Hence, JA may be 0 or 1 (that is, X) and KA must be 1.

Flip-Flop B:

The primary state is 0 and this remains unchanged after the clock pulse. Hence, JB   must be 0 and KB may be 0 or 1 (i.e. X). In the subsequent state 0 changes to 1 after the clock pulse. Hence, JB must be 1 and KB may be 0 or 1 (that is, X).

Flip-Flop C:

The primary state is 0 and this remains unchanged after the clock pulse. Hence JC must be 0 and KC may be 0 or 1 (that is, X). In the subsequent state, this remains unchanged after the clock pulse. Thus, JC must be 0 and KC may be 0 or 1 (that is, X).The JK inputs needed for such have been found with the help of the excitation table, (as in table no.1). The flip-flop input values are entered into Karnaugh maps demonstrated in Fig. a [(i), (ii), (iii), (iv), (v) and (vi)] and a Boolean expression is determined for the inputs to the three flip-flops and then all expressions are simplified. As all the counter states have not been utilized, Xs (don't) are entered to denote un-utilized states. The expressions that simplified for each input have been demonstrated under each map. At last, these minimal expressions for the flip-flop inputs are utilized to draw a logic diagram for the counter demonstrated in fig.(b).

As before, the JK inputs needed for this have been found with the help of the excitation table, (as in table no.1). Such input values are entered in Karnaugh maps Fig. (a)[i to vi] and a Boolean expression is determined for the inputs to the three flip-flops and then all expressions are simplified. Xs have been entered in that counter states that have not been utilized. The simplified expressions for all inputs have been demonstrated under each map and at last a logic diagram based upon these expressions is drawn and is demonstrated in fig.(b).

983_Karnaugh Maps for JA,KA,JB,KB,JC,KC.png

1325_Karnaugh Maps for JA,KA,JB,KB,JC,KC1.png

Fig.(b) Karnaugh Maps for JA,KA,JB,KB,JC,KC

1472_Logic Diagram for MOD-6 Synchronous Counter.png

Fig.(c) Logic Diagram for MOD-6 Synchronous Counter

Posted Date: 5/4/2013 2:53:48 AM | Location : United States







Related Discussions:- Design a mod-6 synchronous counter, Assignment Help, Ask Question on Design a mod-6 synchronous counter, Get Answer, Expert's Help, Design a mod-6 synchronous counter Discussions

Write discussion on Design a mod-6 synchronous counter
Your posts are moderated
Related Questions
Q.  Develop a Menu driven program with following menu: 1.  Gray code 2.  BCD 3.  Excess-3 code 4.  Exit I/P must be a valid Binary number. Fractional numbers are all

What is the Analysis Techniques Object Modelling Object modelling is very significant for any object oriented development, object modelling shows static data structure of real

Q. Explain about Floating-Executive model? Floating-Executive model: The master-slave kernel model is too restrictive in sense that only one of processors viz designated master

What are several issues for selecting best workarounds in multiple inheritances? Some restrictions methods are used. Use two approaches of delegations, which is an implementati

KK manufacturing company is faced with demand for its product in each of the next four periods as shown in Table 1.  It must decide upon a production schedule to meet these demands

Q. Explain the Memory Transfer process? Memory Transfer Transfer of information from memory to outside world which implies I/O Interface is known as a read operation. Tra

Q. Explain the following: a. BCD code b. Gray code c. Excess-3 code d. True complement method Q. Addition-Subtraction-Multiplication-Division: Perform Binary Addi

Explain Lexical substitution during macro expansion ? Lexical substitution is used to produce an assembly statement from a model statement. Model statements have 3 kinds of str

Give the circuit of a TTL NAND gate and explain its operation in brief. Ans: Operation of TTL NAND Gate: Fig.(d) Demonstrates a TTL NAND gate with a totem pole output.

State about CSMA/CA It belongs to a class of protocols known as multiple access methods. CSMA/CA  stands  for:  Carrier  Sense  Multiple  Access  with  Collision Avoidance.  In