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Can you list out some of enhancements in Verilog 2001?
In earlier version of Verilog, we use 'or' to specify more than one element in sensitivity list. In Verilog 2001, we can use comma as represented in the illustration below.
// Verilog 2k example for usage of comma
always @ (i1,i2,i3,i4)
Verilog 2001 allows us to use star in sensitive list rather than listing all the variables in RHS of combo logics. This removes typo mistakes and hence avoids simulation and synthesis mismatches,
Verilog 2001 allows port direction and data type in the port list of modules as represented in the instance below
module memory (
input r,
input wr, input [7:0] data_in,
input [3:0] addr,
output [7:0] data_out
);
Width elements of ports, wire or reg declarations require a constant in both LSB and MSB . Before Verilog 2001, it's a syntax error to specify a function call to evaluate the value of these widths. For instance, following code is erroneous before Verilog 2001 version.
difference between pure and impute inter preter
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