Block schematic diagram of ss7, Electrical Engineering

Q. Block schematic diagram of SS7?

Levels are as below:

Level 1: The Physical Layer
Level 2: The Data Link Level
Level 3: The signaling network level
Level 4: The User Part

Relationship between these levels and the layers of OSI model is displayed in Figure. User part encompasses layers 4 to 7 of OSI model.

1837_Block schematic diagram of SS7.png

Level 1 is means of sending bit streams over a physical path. It uses times lot 16 of a 2 M bit/s PCM system or times slot 24 of a1.5 M bit/s system.

Level 2 performs functions of error control, error rate monitoring, link initialization, delineation of messages andflow control.

Level 3 provides functions essential for a signaling network. Every node in the network has a single point odd that is a 14 bit address. Every message comprises point codes of the originating and terminating nodes for those messages.

Levels 1 to 3 form message transfer part (MTP) of CCITT no. 7.

Level 4 is user part. This comprises the processes for handling the service being supported by signaling system. Message transfer part is capable of supporting many different user parts. So far, three have been defined: telephone user part (TUE), data user part(DUP) and (ISDN) user part (ISDN-UP).

Posted Date: 8/23/2013 1:45:44 AM | Location : United States

Related Discussions:- Block schematic diagram of ss7, Assignment Help, Ask Question on Block schematic diagram of ss7, Get Answer, Expert's Help, Block schematic diagram of ss7 Discussions

Write discussion on Block schematic diagram of ss7
Your posts are moderated
Related Questions
Explain Noise Noise is unwanted signals which degrade the desired signal content and therefore the performance of the system. Noise might be produced either externally or inte

Q. A two-pole, three-phase synchronous generator has a balanced three-phase winding with 15 turns per phase. If the three-phase currents are given by i a = 100 cos 377t, i b =

Cite a specific example in which the engineer must provide maximum efficiency for a given cost

Q. Consider the non inverting amplifier. Let R i = 1k and R f = 2k. Let the op amp be ideal, except that its output cannot exceed ±12 V at a current of ±10 mA. (a) Find the

Differentiate between n and p type semiconductors. n - Type semiconductor:- (i) If small amount of pentavalent impurity is added with, to a pure semiconductor giving a la

Circuit with inductive load  Electromagnetic induction When a conductor is moved across a magnetic field so as to cut by the lines of force (or flux, an electromotive force

A single phase line has an impedance of 8.4 + j11.2 ?. The line feeds a load consisting of a resistor and an inductor connected in parallel as shown in Figure 1. The load is absorb

What is the main difference between 16 bit and 32 bit versions of C/C++ while using in line assembler. The 32-bit applications are written by using Microsoft Visual C/C++ for t

(a) What is understand by clipping circuit. Draw and illustrate different types of diode clipping circuits? (b) With the help of circuit diagram describe the working of centre t