Asynchronous and synchronous logic design, Electrical Engineering

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One of the simplest circuits is the asynchronous or ' ripple' counter. Below is shown the circuit diagram of a simple 3 stage ripple counter.

1234_Asynchronous and Synchronous logic design.png

The operation of this circuit is based on the fact that the truth table for the JK flip flop is only valid if the clock waveform is falling, i.e. 1->0. Assume the outputs are all zero, the flip flops will not change until the clock on each flip flop falls. The clock in waveform has just fallen  ,since the JKa inputs are logic '1' the device will toggle and the output will invert i.e. Qa=1. Flip flop B will not change because the clock waveform on B has risen    (0->1) and these devices only functions on a falling edge. The clock in waveform has fallen again, so Qa toggles again (i.e. Qa =0), this has just produced a falling clock on JKb and Qb toggles (i.e. Qab=1) .The device has just counted from 000-> 001->010.

960_Asynchronous and Synchronous logic design1.png

The circuit is called a ripple counter because the clock pulse is slowly rippling through the JK's, hence asynchronous (Not at the same time!) .The limitations of the asynchronous counter is the speed of operation. A rough formula for the maximum speed is when the clock changes before the output changes i.e.

      F =  1 / n x propagation delay
 
   where n = number of stages, propagation delay of one JK

A better technique is to use a synchronous design where all the JK are clocked together so the maximum frequency is only limited by the propagation delay of 1 JK.  

59_Asynchronous and Synchronous logic design2.png

 
The circuit appears to be complex in design, however it is easily realised by using state diagrams. The maximum frequency of operation is again roughly calculated by considering the frequency at which the output just changes before the clock in changes.
    
      F = 1/ Propagation delay


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