Architecture of 8088-microprocessor, Assembly Language

Architecture Of 8088

The register set of 8088 is accurately the same as in to 8086. The architecture of 8088 is also same to 8086 except for 2 changes; a) 8088 has 4-byte instruction queue and b) 8088 has 8-bit data bus. The function of particular block is the similar as in 8086.the 8088 architecture is shown in figure.

273_arch of 8088.jpg

                                                           Figure: Architecture of 8088

 

The addressing capability of 8088 is 1Mbyte, so, it needs 20 address bits, for example 20 addressing lines. When  handling  this 20-bit  address,  the segmented  memory  scheme  is utilized  and  the total  physical address  forming  procedure  is  the  similar as  explained  in  case  of  8086.  Memory addressingand organization methods of 8088.Whereas physically interfacing memory to 8088, there is nothing such as an even address bank or odd address bank. The total memory is homogeneously addressed as a bank of 1Mbyte memory locations by using the segmented memory scheme. This change in hardware is totally transparent to software.  As a conclusion of the modified data bus, the 8088 may access just a byte at a time. This fact reduces the speed of operation of 8088 as compared to 8086, but the 8088 mayprocess the 16-bit data internally. On account of this change in bus structure, the 8088 has different timing diagrams than 8086.

 

Posted Date: 10/10/2012 3:26:26 AM | Location : United States







Related Discussions:- Architecture of 8088-microprocessor, Assignment Help, Ask Question on Architecture of 8088-microprocessor, Get Answer, Expert's Help, Architecture of 8088-microprocessor Discussions

Write discussion on Architecture of 8088-microprocessor
Your posts are moderated
Related Questions
You have to write a subroutine (assembly language code using NASM) for the following equation.

Compute the Fibonacci sequence - assembly program: Problem: Fibonacci   In this problem you will write a program that will compute the first 20 numbers in the Fibonacci sequ

Physical Memory Mapped I/O and Port I/O : CPU controlled I/O comes in 2 ways. Simply the difference is whether we utilize the normal memory addresses for I/O, this is mention

IRET : Return from ISR:- When an interrupt service routine is called, before transferring control to it, the IP, CS  register and flag registers are stored in the stack to ment

Why is the capability to relocate processes desirable?


Develop an assembly language program for the system and simulate it using MPLAB. From this produce a demo program (in Assembly language) that will run on the MatrixMultimedia Devel

1. Start your program at address $8500. To do this you need to inform the assembler, through the EQU and ORG assembler directives, that you want your program to start at $8500. Thi

Intel's 8237 DMA controller : 1) The 8237 contain 4 independent I/O channels 2) It contains 27 registers, 7 of which are system-wide registers and 5 for each channel. 3)

You will need to upload your main.c and factorial.s files and a .jpg photo of the output on your board using the Vista assignment upload features.  It must be submitted by the dead