Reference no: EM131114159
Show the schematic arrangement for: (a) one dimensional addressing, and (b) two-dimensional addressing (see Problem 6.2.45), if a 32-kbit ROM is used to provide an 8-bit output word.
Problem 6.2.45
Suppose a ROM holds a total of 8192 bits.
(a) How many bits long would the individual addresses have to be?
(b) If the bits are organized into 8-bit memory words or bytes, how many words would there be, and how many bits long would the addresses have to be?
(c) How is such a ROM described?
(d) If each location requires its own word line emanating from a decoder AND gate, how many gates would the decoder for 1K-byte ROM have to contain?
(e) Develop a two-dimensional addressing system using a 6-to-64 decoder, a 64-word×128- bit matrix, and 16-input multiplexers. How many gates would such a system require?
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