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Figure shows a commonly used circuit of a D flip-flop that is triggered by the negative-going edge of the clock φ.
(a) For φ high, what are the values of Q and Q in terms of D? Which transistors are conducting?
(b) If Dis high and φ goes low, which transistors conduct and what signals appear at Q and at Q? Describe the circuit operation.
(c) Repeat (b) for D low with the clock φ going low.
(d) Does the operation of this circuit rely on charge storage?
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The inverters have (W/L)n = 0.2 μm/0.13 μm and (W/L)p = 0.8 μm/0.13 μm. The four NMOS transistors in the set-reset circuit have equal W/L ratios. Determine the minimum value required for this ratio to ensure that the flip-flop will switch.
Transistors Q10, Q11, and Q13 are to be identical and must have the same gm as Q8 and Q9. Transistor Q12 is to be four times as wide as Q13. Let k1n =3k1p =180 μA/V2, and Vtn |Vtp |= 0.5 V; let all hannel lengths be equal; and let VDD =VSS =1.5 V..
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