Segment registers-microprocessor, Assembly Language

Segment Registers

The 8086 addresses a segmented memory unlike 8085. The complete 1 megabyte memory, which 8086 is capable to address is divided into 16 logical segments.Thuseach segment has 64 Kbytes of memory. There are 4 segment registers, viz, Data Segment Register (DS), Code Segment Register (CS), and Segment Register (SS). AndExtra Segment Register (ES) Stack The code segment register is utilized for addressing a memory location in the code segment of the memory, where the executable program is stored. As similar, the data segment register points to the data segment of the memory, where the data is resided. The additional segment also refers to a segment which really is another data segment of the memory. Thus the additional segment also contains data. The stack segment register is utilized for addressing stack segment of memory. The stack segment is that type segment of memory which is utilized to store stack data. The CPU utilizes the stack for provisionally storing important data, for example the contents of the CPU register which will be needed at a later stage. The stack grows down, for example. the data is pushed onto the stack in the memory locations with decreasing addresses.  When this information will be needed by the CPU, they will be popped off from the stack. When addressing of any location in the memory bank, the physical address is computed from 2 parts, the first is segment address and the second offset.  The segment registers contain 16-bit segment base addresses, related to different type of segments. Any of the pointers,BX andindex registers can contain the offset of the location to be addressed. The benefit of this scheme is that in place of maintaining a 20-bit register for a physical address, the processor only maintains two 16-bit registers which are within the word length capacity of the machine. Thus the DS, CS, SS and ES segment registers respectively contain the segment addresses for thedata, code, stack and extra segments of memory. It can be noted that all these segments are the logical segments. They can or cannot be physically separated. In other terms, a single segment may require more than one memory chip or more than 1 segment may be accommodated in a single memory chip.

 

Posted Date: 10/10/2012 4:18:41 AM | Location : United States







Related Discussions:- Segment registers-microprocessor, Assignment Help, Ask Question on Segment registers-microprocessor, Get Answer, Expert's Help, Segment registers-microprocessor Discussions

Write discussion on Segment registers-microprocessor
Your posts are moderated
Related Questions
The modes are determined by the contents of the control register, whose format is given in Figure These modes are: Mode 0: If a group is in mode 0, it is divided into 2 sets.

8237 modes : Intel 8237 can be set to four different type of style of transfer: 1) Single - One transfer at a time,  it allow processor access to the bus between transfers


For an 8088 the 2 addresses linked with an 8259A are normally consecutive, and the AO line is associated to the AO pin, but because there are just 8 data pins on the 8259A and the

RICS/CISC Architecture An essential aspect of computer architecture is the design of the instruction set for the processor.  The instruction set selected for a specific compute

The Alpha : The development of the Alpha chip start in the year 1988 The new chip used 64 bit technology, let users to pack  more  complexity  into  their  programs  than  exis

Internal Architecture of Microprocessor : The architecture of 8086 provides a number of improvements over 8085 architecture. It supports a, a set of 16-bit registers ,16-bit AL

Port Mapped I/O or I/O Mapped I/O I/O devices are mapped into a separate address space. This is generally accomplished by having a different set of signal lines to denote a mem

I need to generate a random number bby using 8086 assembly language

Power Pc : A Power PC is a microprocessor designed to meet a standard, which was combining designed by Motorola, Apple and IBM. The PowerPC standard specifies a common instruc